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netX 50 – networX on chip – The future of communication

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titleUse Case
  • Slave application
netX51 is designed for slave application
  • Companion Chip
With it‘s 32 bit host interface it‘s a fast solution for companion chip solutions
  • Single Chip Solution
Has external memory controller for large applications
  • IO-Link Gateway
Has internal IO-Link Controller
  • EtherCAT
netX 50 has 8 FMMU / 8 Sync Manager compared to netX 100/500
3 FMMU / 4 Sync
  • Don't use for new designs take netX 51 / 52
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titleProtocol Stack availability
ProtocolMasterLinkSlaveLink
As-Interface(minus)ASM2V1(minus)-
CANopen(minus)COM2V9(plus)COS3V1
CC-Link(minus)-(plus)CCS2V7
DeviceNet(minus)DNM2V3(plus)DNS2V3
EtherCAT(minus)ECM3V0(plus)EtherCAT Slave
Ethernet/IP(minus)EIM2V4(plus)EIS2V7
OpenModbus TCP(minus)OMB2V5(plus)OMB2V5
Powerlink(minus)-(plus)PLS2V1
PROFIBUS(minus)DPM2V5(plus)DPS2V4
PROFINET(minus)PNM2V6(plus)PNS3V5
Sercos(minus)S3M2V0(plus)S3S3V1
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DescriptionLink
Development BoardsNXHX 50-ETM
Sales Informationhttp://www.hilscher.com/
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The netX is a highly integrated network controller with a new system architecture optimized for communication and maximum data throughput.

Via an integrated dual-port memory it works as an companion chip to a host CPU and realises the complete scope of industrial communication from fieldbus systems up to the Real-Time Ethernet systems. Allows the application no own CPU the host interface can be configured as Extension Bus or directly as digital input and output. The 32-Bit CPU ARM 966E-S is clocked with 200 MHz and has 112 KB internal RAM and 64 KByte ROM memory. The memory can be expanded flexible by the 32-Bit memory controller with SDRAM, SRAM or FLASH externally. Extensive periphery functions, serial interfaces such as UART, USB, SPI, I²C, as well as the integrated IO-Link and CCD controller allows a large scope of applications. The central data switch and the free configurable communication channels with its own intelligence are the unique selling proposition of the netX as an “high end” network controller.

The data switch connects via five data paths to the ARM CPU and the communication, Host and DMA controllers with the memory or the peripheral units. In this way the controllers transmit their data in parallel, contrary to the traditional sequential architecture with only one common data bus and additional bus allocation cycles.

The controllers of the two communication channels are structured on two levels and are identical to each other. They consist of dedicated ALUs and special logic units that receive their protocol functions via Microcode. For Ethernet the PHYs are integrated which means that the external circuit for Ethernet is reduced to passive componets: transformer and RC components. The Medium-Access-Controller xMAC sends or receives the data according to the respective bus access process and encrypts or converts these into Byte depictions. The Protocol Execution Controller xPEC compiles these into data packets and controls the telegram traffic. Large data amoutns are exchanged in DMA blocks over the memory of the ARM. In addition, every channel has a Dual-port-memory available for status information. Alternatively a triple buffer logic is implemented for a conflict free data exchange which always gives the address of the next free buffer.

With the intelligent communication ALUs, the netX carries out the most varied protocols and protocol combinations on one chip – an absolutely new feature in industrial communication technology.

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netX 50 - Details

Technical Specifications

 

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ARM 966E-S, 200 MIPS, ARMv5TE-command set with DSP-extension

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Ethernet Interface

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2 x 10BASE-T / 100BASE-TX, half/ full duplex, IEEE 1588 time stamp

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EtherCAT with eight FMMUs and eight sync managers
EtherNet/IP
Modbus IDA
POWERLINK with integrated hub
PROFINET RT and IRT with integrated switch
sercos
VARAN

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Periphery

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8 / 16 / 32-bit data bus, 64 KByte configurable in 8 blocks, emulated via internal RAM

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titleBlock diagram

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