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| Core | |||
|---|---|---|---|
| Processor | ARM 966E-S, 200 MIPS, ARMv5TE-command set with DSP-extension | ||
| Internal memory | |||
| RAM | 96 KByte | ||
| ROM | 64 KByte with boot loader | ||
Ethernet Interface | |||
| Port | 2 x 10BASE-T / 100BASE-TX, half/ full duplex, IEEE 1588 time stamp | ||
| PHY | Integrated, auto negotiation, auto crossover | ||
| Real-Time-Ethernet | EtherCAT with eight FMMUs and eight sync managers | ||
| Fieldbus Interface | If Ethernet is not used, the communication channels are available as Fieldbus-Interfaces | ||
| Fieldbus | The systems can be freely combined. AS-interface, Master, only CANopen, Slave CC-Link, Slave, only CompoNet, Slave, only DeviceNet, Slave PROFIBUS, Slave | ||
Periphery | |||
| IO-Link controller | 8 channels, automatically direction control | ||
| CCD sensor controller | Max. 50 MHz, 640x480 Pixel, free configurable data format | ||
| IEEE 1588 system time | 32 bit second counter, 32 bit nanosecond counter | ||
| USB | Revision 1.1, 12 MBaud Full-Speed, host or device mode | ||
| UART | 16550-compatible, max. 3 MBaud, RTS / CTS support | Quantity | 3 |
| I²C | |||
| SPI | Master- and Slave-Mode, max. 10 MHz, 3 Chip-Select-Signals | ||
| General IOs | 3.3 V / 6 mA | Quantity | 32 |
| Status LEDs | 2 LEDs two-colors, 3.3 V / 9 mA | Quantity | 2 |
| Memory interface | |||
| Memory bus | 32 bit data bus / 24 bit address bus | ||
| Address region | 256 MByte SDRAM / 64 MByte Flash | ||
| Memory modules | SDRAM, SRAM, Flash | ||
| Host Interface | |||
| Dual-port memory mode | 8 / 16 / 32-bit data bus, 64 KByte configurable in 8 blocks, emulated via internal RAM | ||
| Extension mode | 8 / 16 / 32-bit data bus, 24-bit address bus, adjustable bus timing | ||
| PIO mode | Freely programmable inputs and outputs | Quantity | 53 |
| Debug Interface | |||
| JTAG | ARM processor and boundary scan | ||
| ETM | Embedded Trace Macrocell, ETM9 V2 Medium Size | ||
| Operating Conditions, Housing, Miscellaneous Data | |||
| System cycle | 200 MHz ARM / 100 MHz Periphery | ||
| Signal level | V | 3.3 | |
| Power supply | for core | V | 1.5 |
| for inputs/outputs | V | 3.3 | |
| Operating temperature | without heat sink | °C | –40 ... +70 |
| with heat sink 10°/W | °C | –40 ... +85 | |
| Storage temperature | °C | –65 ... +150 | |
| Power consumption | PHYs switched off, typically | W typ. | 0.8 |
| PHYs switched on, typically | W typ. | 1.2 | |
| Housing | PBGA, 1 mm raster | pins | 324 |
| Dimensions | mm | 19 x 19 | |
Product Overview
Product | Part Number | Description |
|---|---|---|
| netX 50 | 2230.000 | netX 50 network controller |
Note: When using a Hilscher Master Protocol, a Master license must be separately ordered. It will be delivered in the form of a Security EPROMs, and is foreseen for the design. For further information, please refer to www.hilscher.com/netx