netX 50 – networX on chip The future of communication
Highlights
Flexible “high end” network controller with host interface or single chip solution for digital I/Os
Two communication channels as Real-Time Ethernet with PHY or fieldbus
New system architecture optimized for communication and high data throughput
32-Bit / 200 MHz CPU ARM 966 with 112 KB SRAM / 64 KB ROM and extensive periphery
Dual-Port-Memory, Extension bus or digital I/Os
IO-Link Controller, 8 channels
CCD-Sensor Controller
Block Diagram
Supported Protocols
| Real-Time Ethernet | Fieldbus | Serial |
|---|---|---|
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netX 50
The netX is a highly integrated network controller with a new system architecture optimized for communication and maximum data throughput.
Via an integrated dual-port memory it works as an companion chip to a host CPU and realises the complete scope of industrial communication from fieldbus systems up to the Real-Time Ethernet systems. Allows the application no own CPU the host interface can be configured as Extension Bus or directly as digital input and output. The 32-Bit CPU ARM 966E-S is clocked with 200 MHz and has 112 KB internal RAM and 64 KByte ROM memory. The memory can be expanded flexible by the 32-Bit memory controller with SDRAM, SRAM or FLASH externally. Extensive periphery functions, serial interfaces such as UART, USB, SPI, I²C, as well as the integrated IO-Link and CCD controller allows a large scope of applications. The central data switch and the free configurable communication channels with its own intelligence are the unique selling proposition of the netX as an “high end” network controller.
The data switch connects via five data paths to the ARM CPU and the communication, Host and DMA controllers with the memory or the peripheral units. In this way the controllers transmit their data in parallel, contrary to the traditional sequential architecture with only one common data bus and additional bus allocation cycles.
The controllers of the two communication channels are structured on two levels and are identical to each other. They consist of dedicated ALUs and special logic units that receive their protocol functions via Microcode. For Ethernet the PHYs are integrated which means that the external circuit for Ethernet is reduced to passive componets: transformer and RC components. The Medium-Access-Controller xMAC sends or receives the data according to the respective bus access process and encrypts or converts these into Byte depictions. The Protocol Execution Controller xPEC compiles these into data packets and controls the telegram traffic. Large data amoutns are exchanged in DMA blocks over the memory of the ARM. In addition, every channel has a Dual-port-memory available for status information. Alternatively a triple buffer logic is implemented for a conflict free data exchange which always gives the address of the next free buffer.
With the intelligent communication ALUs, the netX carries out the most varied protocols and protocol combinations on one chip – an absolutely new feature in industrial communication technology.
netX 50 - Details
Technical Specifications
| Core | |||
|---|---|---|---|
| Processor | ARM 966E-S, 200 MIPS, ARMv5TE-command set with DSP-extension | ||
| Internal memory | |||
| RAM | 96 KByte | ||
| ROM | 64 KByte with boot loader | ||
Ethernet Interface | |||
| Port | 2 x 10BASE-T / 100BASE-TX, half/ full duplex, IEEE 1588 time stamp | ||
| PHY | Integrated, auto negotiation, auto crossover | ||
| Real-Time-Ethernet | EtherCAT with eight FMMUs and eight sync managers | ||
| Fieldbus Interface | If Ethernet is not used, the communication channels are available as Fieldbus-Interfaces | ||
| Fieldbus | The systems can be freely combined. AS-interface, Master, only CANopen, Slave CC-Link, Slave, only CompoNet, Slave, only DeviceNet, Slave PROFIBUS, Slave | ||
Periphery | |||
| IO-Link controller | 8 channels, automatically direction control | ||
| CCD sensor controller | Max. 50 MHz, 640x480 Pixel, free configurable data format | ||
| IEEE 1588 system time | 32 bit second counter, 32 bit nanosecond counter | ||
| USB | Revision 1.1, 12 MBaud Full-Speed, host or device mode | ||
| UART | 16550-compatible, max. 3 MBaud, RTS / CTS support | Quantity | 3 |
| I²C | |||
| SPI | Master- and Slave-Mode, max. 10 MHz, 3 Chip-Select-Signals | ||
| General IOs | 3.3 V / 6 mA | Quantity | 32 |
| Status LEDs | 2 LEDs two-colors, 3.3 V / 9 mA | Quantity | 2 |
| Memory interface | |||
| Memory bus | 32 bit data bus / 24 bit address bus | ||
| Address region | 256 MByte SDRAM / 64 MByte Flash | ||
| Memory modules | SDRAM, SRAM, Flash | ||
| Host Interface | |||
| Dual-port memory mode | 8 / 16 / 32-bit data bus, 64 KByte configurable in 8 blocks, emulated via internal RAM | ||
| Extension mode | 8 / 16 / 32-bit data bus, 24-bit address bus, adjustable bus timing | ||
| PIO mode | Freely programmable inputs and outputs | Quantity | 53 |
| Debug Interface | |||
| JTAG | ARM processor and boundary scan | ||
| ETM | Embedded Trace Macrocell, ETM9 V2 Medium Size | ||
| Operating Conditions, Housing, Miscellaneous Data | |||
| System cycle | 200 MHz ARM / 100 MHz Periphery | ||
| Signal level | V | 3.3 | |
| Power supply | for core | V | 1.5 |
| for inputs/outputs | V | 3.3 | |
| Operating temperature | without heat sink | °C | –40 ... +70 |
| with heat sink 10°/W | °C | –40 ... +85 | |
| Storage temperature | °C | –65 ... +150 | |
| Power consumption | PHYs switched off, typically | W typ. | 0.8 |
| PHYs switched on, typically | W typ. | 1.2 | |
| Housing | PBGA, 1 mm raster | pins | 324 |
| Dimensions | mm | 19 x 19 | |
Product Overview
Product | Part Number | Description |
|---|---|---|
| netX 50 | 2230.000 | netX 50 network controller |
Note: When using a Hilscher Master Protocol, a Master license must be separately ordered. It will be delivered in the form of a Security EPROMs, and is foreseen for the design. For further information, please refer to www.hilscher.com/netx