IO Library / Pad Cell
- André Groß
How does a pad work and what can be configured?
A register in the pad_ctrl device represents each pad internally. These registers are available via the internal data bus in the pad_ctrl. The following image shows the register definition of pad B11 or HIF_D0. This register contains the state of the pad. Several configuration parameters are configurable.
The next picture shows the pads circuit. The pad is on the right side of the circuit. On the left side, there are the internal signals of the pad.
The drive strenght DS is a configuration signal of the output driver. The drive strength might vary between 2mA and 16mA. The most pads in use have a drive strength of 4mA and 8mA. The drivers might have a slew rate control included or not. This pad has not. There would be a symbol with a rising edge inside the driver icon. The output enable negated OEN will activate or deactivate the driver. If the driver is not active the cell is input and thus in a high impendance state called Z.
If the cells output is enabled the cells input I is driven by the driving circuit with the given drive strength. This is either high 1 or low 0.
The pull enable PE activates or deactivates an internal resistor. Depending on the pad type it is either a Pull-High H or a Pull-Low L.
The input enable IE activates or deactivates the trigger of the pad cell. This might be just a simple threshold or could be a Schmitt Trigger. In this case it is a Schmitt Trigger.
The C signal is the internal signal of the pad cell. It is the "input" of the cell represented as a logical value.
In the following table 0/1 is don’t care and X is Unknown state.
Truth table of the pad cell shown above:
| INPUT | OUTPUT | ||||||
|---|---|---|---|---|---|---|---|
| DS | OEN | I | PAD | PE | IE | PAD | C |
| 0/1 | 0 | 0 | - | 0/1 | 0 | 0 | 0 |
| 0/1 | 0 | 0 | - | 0/1 | 1 | 0 | 0 |
| 0/1 | 0 | 1 | - | 0/1 | 0 | 1 | 0 |
| 0/1 | 0 | 1 | - | 0/1 | 1 | 1 | 1 |
| 0/1 | 1 | 0/1 | 0 | 0/1 | 0 | - | 0 |
| 0/1 | 1 | 0/1 | 0 | 0/1 | 1 | - | 0 |
| 0/1 | 1 | 0/1 | 1 | 0/1 | 0 | - | 0 |
| 0/1 | 1 | 0/1 | 1 | 0/1 | 1 | - | 1 |
| 0/1 | 1 | 0/1 | Z | 0 | 0 | - | 0 |
| 0/1 | 1 | 0/1 | Z | 0 | 1 | - | X |
| 0/1 | 1 | 0/1 | Z | 1 | 0 | H | 0 |
| 0/1 | 1 | 0/1 | Z | 1 | 1 | H | 1 |
Which IO Voltages are there?
VDDIO is 3V3
VDDC is 1V2
There are no other voltage levels.
What is the reset behaviour of the Pads?
In the register definition the reset value of the pads is shown. This equals the state after the IO library was configured by the power on reset.
Any not power on reset will not affect the pad cells.
The hardware configuration that is set by the ROM code will alter this reset values.