5.3.2      SQI

5.3.2.8      I/O timing

The SQI_XIP module IO timing differs between peripheral mode (data exchange by the FIFO registers) and XiP mode (reading data from the linear XiP adder area). You must take the values which are related to the mode in you use the module.

5.3.2.8.1        Peripheral mode I/O timing

The following figures show the timing in FIFO/peripheral mode (not in linear addressing XiP mode) for 1 bit SPI.

Regarding the transfer direction, timing parameters are identical for Dual and Quad SPI mode:
In receive mode, timing for sqi_miso can be applied to all I/O lines. In transmit mode, timing for sqi_mosi can be applied to all I/O lines.

Figure 1: SPI timing SPO=0 and SPH=0 transfer (data sampling on rising edge, generation on falling edge of sqi_sck)

Figure 2: SPI timing SPO=0 and SPH=1 transfer (data sampling on falling edge, generation on rising edge of sqi_sck)

Figure 3: SPI timing SPO=1 and SPH=0 transfer (data sampling on falling edge, generation on rising edge of sqi_sck)

Figure 4: SPI timing SPO=1 and SPH=1 transfer (data sampling on rising edge, generation on falling edge of sqi_sck)

SPI timing for worst case operating conditions for peripheral mode (register sqi_sqirom_cfg bit enable is not set): V_DD: 3.0 ... 3.6 V, T_j: -40 … +125°C, C_L: 20 pF. Values in brackets apply if input filtering is enabled. IOs must be programmed for high (8mA) driving mode.

Table 1: Peripheral mode SQI I/O timing parameters

Notes:

1. N is programmed by register spi_cr0, bits sck_muladd. N = 1 ... 2048
2. If bit fss_static is set in register spi_cr1, sqi_fss will not toggle between data words, but a half clock pause will be inserted anyway before the next word MSB.
3. In SPH=1 modes sqi_fss does not become inactive during continuous transfers between LSB and next word MSB.
4. Input filtering can be enabled / disabled by bit filter_in of register spi_cr0.

5.3.2.8.1        SQI XiP mode I/O timing

The following figures show the timing in linear addressing XiP mode (not in FIFO/peripheral mode) which supports only 4 bit mode 0 and 3 with chip-select 0.

Figure 5: XiP timing (data sampling on rising edge, generation on falling edge of sqi_sck)

SPI timing for worst case operating conditions for XiP mode (register sqi_sqirom_cfg bit enable is set): V_DD: 3.0 ... 3.6 V, T_j: -40 … +125°C, C_L: 20 pF, IOs must be programmed for high (8mA) driving mode.

Data is transmitted on the signals SQI_MOSI, SQI_MISO, SQI_SIO2 and SQI_SIO3. MOSI data is transmitted from the netX to the device (i.e. the command word to initiate a read access, not payload data, the memory device can only be programmed in peripheral mode). MISO data is transmitted from the device to the netX (i.e. the data read from the memory).

All signal rise and fall times and clock duty cycle distortions caused by the netX are included in the timing parameters and need not to be considered additionally.

Table 2: XiP mode SQI I/O timing parameters

Notes:

1. N is programmed by register sqi_sqirom_cfg, bits clk_div_val. N = 0..255. This leads to a frequency up to 133 MHz.
2. The chip-select timing of QSPI devices is typically related to the rising clock edge (as described). However, for mode 0 a falling clock edge is generated 0.5*t_CP before chip-select becomes inactive (at transfer end) and for mode 1 and a falling clock edge is generated 0.5*t_CP after chip select becomes active (at transfer start).
3. The min. chip-select idle time can be programmed by bit t_csh of register sqi_sqirom_cfg. Between 1 and 4 SPI clock cycles can be selected (I). The device will not be deselected if no XiP access is desired. The SPI_CLK line will be held inactive instead. To disable the chip-select for longer times (e.g. for power save) switch to peripheral mode. A device will always be selected at least until the first 4 byte of data have been received in quad-IO-read (i.e. at least for 14 serial clock periods with a running serial clock).
4. Input filtering is not available in SQIROM/XiP mode.

Example to determine the maximum frequency for a device:

Assuming a device with the following basic parameters: For read it provides valid output data at time t_DOV = 6.0 ns after the falling (generating) edge of the serial clock. It holds the data stable until t_DOH = 1.0 ns after the next falling clock edge. For write it requires the input data to be setup stable at t_DIS = 2.0 ns before the rising (sampling) edge of the serial clock. Then it must be hold stable until t_DIH = 2.0 ns after this clock edge.

Typically, the read data timing, especially the data-out-valid-time t_DOV, determines the maximum frequency of the serial clock, so look at this first:

According to the table above, the netx requires the data at least 0.9 ns (t_xMISOS) before the rising (sampling) edge and requires the data being stable at least for 1.5 ns (t_xMISOH) after this edge.

The following table shows this and the main other requirements, which have to be considered. It is important to use the correct clock edge relations. Take care: Datasheet may differ here!

Table 3: XiP mode SQI I/O timing parameters

The significant requirement for this case is the first one as it leads to the longest clock period. As the period can only be programmed in steps of 2.5 ns, it must be set to 15.0 ns, i.e. 66.66 MHz. However, before you really select a device you should also look at the other timings e.g. for the chip-select signal.