7.3 Oscillator

Symbol	Parameter	Condition	Min	Typ	Max	Unit
V_{DD_PLL}	Supply voltage PLL	-	1.14	1.2	1.32	V
V_IL	Input voltage, low	Note 1			0.8	V
V_IH	Input voltage, high	Note 1	2.0			V
V_OL	Output voltage, low	+8 mA / Note 1			0.4	V
V_OH	Output voltage, high	-8 mA / Note 1	2.4			V
V_ITH	Input voltage, threshold	-	38	43	48	%V_DDIO
f_CLK	Crystal clock frequency	Note 2		25		MHz
T_CLK	Clock cycle time	-		40		ns
T_CTL	Clock tolerance	-	-50		+50	ppm
T_CDC	Clock duty cycle	Note 2	40	50	60	%
T_PPJ	Peak-to-peak Period Jitter			20	40	ps
T_RPJ	Phase Jitter (Integrated Phase Noise)	Integration bandwidth = 12 kHz to 20 MHz (at f_CLK)		2	5	ps [RMS]
J_LF	Phase Jitter for Low Frequencies	At 12 kHz (Note 3)			-140	dBc/Hz
M_LFS	Slope of Phase Jitter for Low Frequencies	At and below 12 kHz (Note 3)			20	dBc/dec
R_f	Integrated feedback resistor	-	0.97	1.2	1.46	MΩ
C_IN	Pin capacitance OSC_XTI	-	3.4	4	4.6	pF
C_OUT	Pin capacitance OSC_XTO	-	1.7	2	2.3	pF

Table 37: Electrical specification

Note:

These values are DC parameters that do not apply to the dynamical system of a crystal circuit. When using crystals, the circuit should be designed in a way that keeps the levels within the absolute maximum ratings (-0.3 V to V_DDIO +0.3V).
f_CLK must be supplied by crytsal or external oscillator. If external oscillator is used, it is strongly suggested to use a duty cycle better than 45% to 55% with lower jitter performance.
MEMS oscillators have a significantly higher phase noise for low offsets as compared to quartz, especially below 12 kHz. Notably worse phase noise at low offsets is critical for real-time Ethernet communications because it could cause sporadic bit errors.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
V_{DD_PLL} – V_SS	-	-	-0.3	-	1.4	V

Table 38: Absolute maximum ratings