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More Functions and Higher Performance for Real-Time Ethernet

The netX is a highly integrated network controller with a new system architecture optimized for communication and maximum data throughput.

Based on the 32 bit CPU ARM 926EJ-S cycled at 200 MHz, it possesses a memory management unit, caches, DSP and Java extensions. The internal memory of 144 KByte RAM and 32 KByte ROM that contains the boot loader is sufficient for smaller applications whereas for Windows CE and Linux it is supplemented with the 32 bit memory controller memory externally with SDRAM, SRAM or FLASH. The connection to a primary Host is carried out via the dual-port memory interface, which is configurable for stand-alone applications also as a 16 bit extension bus. Comprehensive peripheral functions, serial interfaces such as UART, USB, SPI, I²C as well as the integrated graphic controller permit a wide spectrum of applications. Yet, it is the central data switch and the four freely configurable communication channels with their own intelligence that is the main characteristic of the netX as a "high end” network controller.

The data switch connects via five data paths to the ARM CPU and the communication, graphic and Host controllers with the memory or the peripheral units.

In this way the controllers transmit their data in parallel, contrary to the traditional sequential architecture with only one common data bus and additional bus allocation cycles.

The controllers of the four communication channels are structured on two levels and are identical to each other. They consist of dedicated ALUs and special logic units that receive their protocol functions via Microcode. Two channels posses an additional integrated PHY for Ethernet.

The Medium-Access-Controller xMAC sends or receives the data according to the respective bus access process and encrypts or converts these into byte depictions.

The Protocol Execution Controller xPEC compiles these into data packets and controls the telegram traffic. These are exchanged in DMA blocks over the memory of the ARM. In addition, every channel has a dual-port memory available for status information or as local data image.

With the intelligent communication ALUs, the netX carries out the most varied protocols and protocol combinations and can synchronize them independently of the reaction time of the CPU – an absolutely new feature in industrial communication technology.

Block Diagram

netX 100/500 - Details

Technical Specifications

 netX 100netX 500
Core
Processor

ARM 926EJ-S, 200 MIPS, ARMv5TE-command set with DSP- and Java-extension

X

X

Cache16 KByte commands / 8 KByte dataXX
Tightly coupled memory8 KByte dataXX
Memory Managment UnitWindows CE  and Linux supportXX
Internal memory
RAM144 KByte, of this 16 KByte with external voltage supplyXX
ROM32 KByte with boot loaderXX

Ethernet Interface

Port2 x 10BASE-T / 100BASE-TX, half/ full duplex, IEEE 1588 time stampXX
PHYIntegrated, auto negotiation, auto crossoverXX
Real-Time-Ethernet

EtherCAT with three FMMUs and four sync managers
EtherNet/IP
Modbus IDA
POWERLINK with integrated hub
PROFINET RT and IRT with integrated switch
sercos
VARAN

 

X

 

X

Fieldbus InterfaceIf Ethernet is not used, then one respecively two additional fieldbusses are available
FieldbusThe systems can be freely combined.Quantity12
AS-interface, Master, only
CANopen, Master or Slave
CC-Link, Slave, only
CompoNet, Slave, only
DeviceNet, Master or Slave
PROFIBUS, Master or Slave

 

X

 

X

Peripheral components

Color LCD controller

For TFT-panels, Color-STN- and Mono-STN-panels

Resolution 320 x 200 to 640 x 480, color depth 1, 2, 4, 8, 16-Bit

 X
Real-Time clockWith external voltage supply X
IEEE 1588 system time32 bit second counter, 32 bit nanosecond counterXX
USB

Revision 1.1, 12 MBaud full speed, host or device mode

XX
UART16550-compatible, max. 3 MBaud, RTS / CTS supportQuantity33
I²C XX
SPI

Master- and Slave-Mode, max. 10 MHz, 3 Chip-Select-Signals

XX
AD-Converter

2 x 4 Channels with 1MS/s Sample&Hold and 10 Bit-resolution

Single ended, Common Analog Ground, external reference voltage

XX
PWM0 – 20 kHz /12-Bit-resolution  0 – 80 kHz /10-Bit-resolutionXX
Encoder2 Channels, Impuls quadruplication, digital input filterXX
General IOs3.3 V / 6 mAQuantity1616
Status LEDs2 LEDs dual colored, 3.3 V / 9 mA XX
Memory interface
Memory bus32-Bit-Databus / 24-Bit-Address busXX
Address region256 MByte SDRAM / 64 MByte FlashXX
Memory modulesSDRAM, SRAM, FlashXX
Host Interface
Dual-port memory mode8/16-Bit-Databus, 64 KByte configurable in 8 Blocks; emulated by internal RAMXX
Extension mode8/16 bit data bus, 24 bit address bus, bus timing adjustableXX
PIO modeFreely programmable inputs and outputsQuantity5353
Debug Interface
JTAGARM processor and boundary scanXX
ETMEmbedded Trace Macrocell, ETM9 V2 Medium SizeXX
Operating Conditions, Housing, Miscellaneous Data
System cycle200 MHz ARM / 100 MHz Periphery
Signal level V3.33.3
Power supplyfor coreV1.51.5
for inputs/outputsV3.33.3
Operating temperaturewithout heat sink, circuit board > 30 cm²°C–40 ... +70–40 ... +70
with heat sink 10°/W°C–40 ... +85–40 ... +85
Storage temperature °C–65 ... +150–65 ... +150
Power consumptionPHYs switched off, typicallyW typ.1.01.0
PHYs switched on, typicallyW typ.1.51.5
HousingPBGA, 1.0 mm rasterpins345345
Dimensionsmm22 x 2222 x 22
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