Skip to end of banner
Go to start of banner

Concurrency Insights

Skip to end of metadata
Go to start of metadata

You are viewing an old version of this page. View the current version.

Compare with Current View Page History

« Previous Version 4 Next »

When using an operating system, the scheduler takes over the aspect of concurrency for developers by switching between different tasks back and forth. This method delivers great prospects for developers, since it abstracts many challenges the bare-metal approach possesses by modular, priority based scheduling and simplifying timing requirements.

In a bachelor thesis with the tile: “Evaluation of Concurrent Task Execution in FreeRTOS on a Cortex M4F Architecture”, Mr. Witte determined for Hilscher concurrency aspects of FreeRTOS on a netX 90 device. In the following chapters, the thesis' results are further discussed.


Task Switch Overhead

The central question in Mr. Witte's work was, whether the netX 90 behaves similar to other Cortex M4 platforms when it comes to the generated overhead by FreeRTOS. He defined the Task Switch Overhead (TSO) as “the required time to perform one task switch, which is the transaction time from one task to another”.

Mr. Witte realized that the TSO primarily depends on the used scheduling algorithm and the number of processor registers which are stored on the stack. This is why he measured cooperative and pre-emptive scheduling separately. Moreover, when the FPU is used, additional processor registers are put into operation, which requires the scheduler to store the registers S0 — S31 as well. He concludes that this must take additional time.

In his work, he determined the average context switch overhead for FreeRTOS V10.3.1 to:

  1. Cooperative scheduling concept
    1. ~201 clock cycles without FPU utilization
    2. ~268 clock cycles with FPU utilization
  2. Pre-emptive scheduling concept
    1. ~377 clock cycles without FPU utilization
    2. ~444 clock cycles with FPU utilization



From these findings, he derived the “wasted processor capacity” diagram, which declares that with a certain system tick-rate, the task-switch requires a certain amount of processor capacity. This scales up to the point of which the task-switch cannot be processed before another system tick occurs, which puts the system eventually in a freezing state.

  • No labels