netX 500

More Functions and Higher Performance for Real-Time Ethernet

Highlights

• Flexible “high end” network controller or highly integrated single chip solution for applications and communication
• Four communication channels as Real-Time Ethernet or fieldbusinterface
• individually configurable
• New system architecture optimized for communication and high data throughput
• 32-Bit/200MHz CPU ARM 926
• with 200 MIPs computing power for Windows CE and Linux

• Dual-port memory, AD converter and graphic controller on chip

Block Diagram

Supported Protocols

Real-Time Ethernet	Fieldbus

netX 100/netX 500

The netX is a highly integrated network controller with a new system architecture optimized for communication and maximum data throughput.

Based on the 32 bit CPU ARM 926EJ-S cycled at 200 MHz, it possesses a memory management unit, caches, DSP and Java extensions. The internal memory of 144 KByte RAM and 32 KByte ROM that contains the boot loader is sufficient for smaller applications whereas for Windows CE and Linux it is supplemented with the 32 bit memory controller memory externally with SDRAM, SRAM or FLASH. The connection to a primary Host is carried out via the dual-port memory interface, which is configurable for stand-alone applications also as a 16 bit extension bus. Comprehensive peripheral functions, serial interfaces such as UART, USB, SPI, I²C as well as the integrated graphic controller permit a wide spectrum of applications. Yet, it is the central data switch and the four freely configurable communication channels with their own intelligence that is the main characteristic of the netX as a "high end” network controller.

The data switch connects via five data paths to the ARM CPU and the communication, graphic and Host controllers with the memory or the peripheral units.

In this way the controllers transmit their data in parallel, contrary to the traditional sequential architecture with only one common data bus and additional bus allocation cycles.

The controllers of the four communication channels are structured on two levels and are identical to each other. They consist of dedicated ALUs and special logic units that receive their protocol functions via Microcode. Two channels posses an additional integrated PHY for Ethernet.

The Medium-Access-Controller xMAC sends or receives the data according to the respective bus access process and encrypts or converts these into byte depictions.

The Protocol Execution Controller xPEC compiles these into data packets and controls the telegram traffic. These are exchanged in DMA blocks over the memory of the ARM. In addition, every channel has a dual-port memory available for status information or as local data image.

With the intelligent communication ALUs, the netX carries out the most varied protocols and protocol combinations and can synchronize them independently of the reaction time of the CPU – an absolutely new feature in industrial communication technology.

netX 100/500 - Details

Technical Specifications

Product Overview

Note: When using a Hilscher Master Protocol, a Master license must be separately ordered. It will be delivered in the form of a Security EPROMs, and is foreseen for the design. For further information, please refer to www.hilscher.com/netx

Documentation