CIF - PCI Information

PCI-Register Definition
- CIF50/80 (PLX 9050-Chip and PLX 9030-Chip)
- CIF52/54 (PLX 9030-Chip)

Base Address 0     = Memory Mapped Runtime PCI register
Base Address 1     = I/O Mapped PCI register
Base Address 2     = CIF 50/80 dual ported memory
Base Address 3     = Second dual ported memory on CIF 52/54

Interrupt Pin          = Interrupt enabled / disabled state
Interrupt Line        = Physical interrupt line

Attention:
CIF52 and CIF54 are working with two independend DPM memory areas.
These are the entries of the CIF52 2Channel cards using the PLX 9030 Chip
VENDOR_ID         0x10B5          PLX technology                    
DEVICE_ID         0x9030          PLX-PCI chip                      
SUBVENDOR_ID      0x10B5          PLX technology                    
SUBSYSTEM_ID      0x3060          Defines a HILSCHER CIF 52 PCI board

These are the entries of the CIF54 4Channel cards using the PLX 9030 Chip
VENDOR_ID         0x10B5          PLX technology                      
DEVICE_ID         0x9030          PLX-PCI chip                     
SUBVENDOR_ID      0x10B5          PLX technology                   
SUBSYSTEM_ID      0x2833          Defines a HILSCHER CIF 54 PCI board

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EXAMPLE: INTERRUPT-HANDLING
     CIF50 / CIF80 ONLY
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Desciption:

The PCI-Chip of the CIF 50/80 always request an interrupt resource from the system,
but the physical interrupt generation is disabled.
The reason is to prevent an interrupt generation, by the hardware, before an interrupt service function
is installed. Otherwise the PCI bus can be blocked by an unserviced interrupt, wich will result in an
blocked system (e.g. DOS).

The interrupt will be enabled by writing into a specific area of the PCI register.
This can be done either by writing to a memory location or into an IO port address, depending where the
PCI registers are mapped. Both ways are supported by CIF 50.

The information where the registers are located can be taken from the PCI Configuration Information structure.

Here is an example, how to generate the real physical address from the PCI Configuration structure
by using "Base Address 1" to access the PCI registers via I/O port addresses.

- Generate the physical address from the PCI Configuration structure
  ulIOLocalRegAddress  = (BaseAddress1 & 0xFFFFFFFE);

- Enable or disable the physical hardware interrupt

//--------------------------------------------------------------
// DriverSetInterruptState
// Enable /Disable PCI Interrupt for CIF50/80
//--------------------------------------------------------------
#define HW_INTERRUPT_DISABLE     0x00
#define HW_INTERRUPT_ENABLE      0x01
/* Local Control Register Offsets */
#define PCI_INTCTRLSTS_REG       0x4C

  unsigned char bData;

  bData = _inp ( ulIOLocalRegAddress + PCI_INTCTRLSTS_REG);

  if ( usIntState == HW_INTERRUPT_ENABLE) {
    // Enable Interrupt (LCR-Registers)
    bData = (unsigned char)(bData | HW_INTERRUPT_ENABLE);
  } else {
    // Disable PCI Interrupt (LCR-Registers)
    bData = (unsigned char)(bData & ~HW_INTERRUPT_ENABLE);
  }
  // Write new data to port
  _outp ( (ulIOLocalRegAddress + PCI_INTCTRLSTS_REG), bData);


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INFORMATION for CIF52 /CIF54
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Desciption:

The CIF 52 and CIF 54 containing two independent CIFs on the local side and handled as
two independent cards.

The second DPM can be found in the PCI "Base Address 3".

Also the interrupt handling is different. While the CIF54 uses only one Interrupt for both DPMs, the
CIF52 uses two independent local interrupt for each interface.
Like on the CIF50/80, the PCI-Chip of the CIF 52/54 always request an interrupt resource from the system,
but the physical interrupt generation is disabled (see CIF50/80).

Interrupt enable on the CIF54 works like on the CIF50/80. The CIF52 needs to enable two local interrupts
The interrupt will be enabled by writing into a specific area of the PCI register (memory mapped or I/O mapped).

Enable interrupt on CIF54 (see CIF50/80).
Enable interrupt on CIF52 needs a second interrupt enable bit set.

//--------------------------------------------------------------
// DriverSetInterruptState
// Enable /Disable PCI Interrupt for CIF52
//--------------------------------------------------------------
#define HW_INTERRUPT_DISABLE         0x00
#define HW_INTERRUPT_ENABLE_CIF52    0x09

/* Local Control Register Offsets */
#define PCI_INTCTRLSTS_REG       0x4C

  unsigned char bData;

  bData = _inp ( ulIOLocalRegAddress + PCI_INTCTRLSTS_REG);

  if ( usIntState == HW_INTERRUPT_ENABLE_CIF52) {
    // Enable Interrupt (LCR-Registers)
    bData = (unsigned char)(bData | HW_INTERRUPT_ENABLE_CIF52);
  } else {
    // Disable PCI Interrupt (LCR-Registers)
    bData = (unsigned char)(bData & ~HW_INTERRUPT_ENABLE_CIF52);
  }
  // Write new data to port
  _outp ( (ulIOLocalRegAddress + PCI_INTCTRLSTS_REG), bData);