This page will be made public until end of Q2 2022 when the PCN for the ROM code change is released; see ROM: Root of trust necessary to hardening the embedded system do not enable IEC 62443 compliant security levels higher than SL 2
Product Revision | Maskset Type | Version Register1) | Mass Production | ROM Code Revision | Ethernet PHY Revision2) | Date Code YYWW3) |
|---|---|---|---|---|---|---|
netX 90 Rev.0 | Single Layer Mask (SLM) | 0x0900000d | No | 0x0 | 0x2 | 1830 ≤ YYWW < 1910 |
netX 90 Rev.1 | Revised Tape Out (RTO) | 0x0900010d | Yes | 0x1 | 0x2 | 1910 ≤ YYWW < 2111 |
0x3 (PCN 200230) | 2111 ≤ YYWW ≤ 22xx | |||||
| netX 90 Rev.2 | Revised Tape Out (RTO) | 0x0901020d | Yes | 0x2 (PCN 220093) | 0x3 | 22xx ≤ YYWW |
Table 1: netX 90 revision history
Note 1:
| R/W | 0x0000000d | Address : 0xff401298 | |
| Bits | Reset Value | Description | Remark |
|---|---|---|---|
| 31 - 24 | 0x0 | Hilscher file header version | ROM code writes value 0x9 for netX 90 during boot sequence |
| 23 - 16 | 0x0 | Chip-specific revision | ROM code defines and writes this value during boot sequence |
| 15 - 8 | 0x0 | ROM code revision | ROM code defines and writes this value during boot sequence |
| 7 - 0 | 0xd | Chip type | Chip type defined at SLM tape out |
Table 2: netX 90 version register
Note 2:
- The 4-bit manufacturer Ethernet PHY revision number, stored in the internal PHY Identifier 2 register of the integrated Ethernet PHY, can be only accessed and read out using the SMI of the xC subsystem.
Note 3:
Figure 1: netX 90 package marking