Revision netX 90

Product Revision	Maskset Type	Version Register¹⁾	Mass Production	ROM Code Revision	Ethernet PHY Revision²⁾	Date Code YYWW³⁾	Lot Trace Code LL³⁾
netX 90 Rev.0	Single Layer Mask (SLM)	0x0900000d	No	0x0	0x2	1830 ≤ YYWW < 1910	LL = 1
netX 90 Rev.1	Revised Tape Out (RTO)	0x0900010d	Yes	0x1	0x2	1910 ≤ YYWW < 2111	2 ≤ LL ≤ 7
netX 90 Rev.1	Revised Tape Out (RTO)	0x0900010d	Yes	0x1	0x3 (PCN 200230)	2111 ≤ YYWW ≤ 2229	8 ≤ LL ≤ 23
netX 90 Rev.2	Revised Tape Out (RTO)	0x0901020d	Yes	0x2 (PCN 220275)	0x3	YYWW ≥ 2229	LL ≥ 24

Table 1: netX 90 revision history

Note 1:

Bits	Reset Value	Description	Remark
R/W	0x0000000d	Address : 0xff401298
31 - 24	0x0	Hilscher file header version	ROM code writes value 0x9 for netX 90 during boot sequence
23 - 16	0x0	Chip-specific revision	ROM code defines and writes this value during boot sequence
15 - 8	0x0	ROM code revision	ROM code defines and writes this value during boot sequence
7 - 0	0xd	Chip type	Chip type defined at SLM tape out

Table 2: netX 90 version register

Note 2:

The 4-bit manufacturer Ethernet PHY revision number, stored in the internal PHY Identifier 2 register of the integrated Ethernet PHY, can be only accessed and read out using the SMI of the xC subsystem.

Note 3:

netX