Motion Analog-to-Digital Converter (MADC)

Each of the four ADCs of the netX 90 is controlled by an individual MADC module. Each MADC module has its own register read/write bus (cpu_*), irq line (cpu_irq) and AHBL master port to write its measurements to the system memory. Therefore, the software can operate all ADCs completely independently from each other.

The common MADCC module generates the adc_clk_phase signal which schedules the generation of the adc_clk signals among the MADC modules, e.g. to prevent simultaneous occurrence of a rising edge on multiple adc_clks. The MADCC module also provides the static configuration signals to the analogue ADC blocks.

The sampling of the ADCs can be synchronized to the motor PWM  (MPWM) module, either to the phase of the PWM signal (ECNT) or to the start of the dead time (DTEVT) between low and high side.

Figure1: netX90 MADC controller operating environment

Features

• Scalable to any number of SAR ADCs
• Measurement sequencing:
  A measurement sequence consists of up to 8 individually configurable measurements which are executed without software intervention. The measurements are executed sequentially, from the lowest enabled measurement configuration to the highest. When the measurement sequence has completed irq MPWM_IRQ_RAW.ms_evt is asserted.
• Single shot and continuous conversion:
  The measurement sequence can be executed once (single shot) or continuously until stopped by software.
• Double buffering:
  The configuration registers for the measurement sequence and all measurements are double buffered by means of shadow registers which are transferred to the configuration registers when a measurement sequence has been completed or at the request of software. Thus, the next measurement sequence can be set up during processing of the current.
• Measurement functionality:
  • Averaging by summing:
    Each measurement performs MADC_M number of ADC conversions which are summed to average out noise. No division is performed.
  • Sampling extension:
    One of 4 configurable sampling extensions can be selected for each measurement to adapt the minimum length of the sampling phase to the impedance of the measured analogue signal source.
  • Synchronised and non-synchronized sampling:
    The sampling can be synchronized with the MPWM module. The sampling can either occur at a specific time of the MPWM period (ECNT) or occur after a programmable delay after one of the 6 dead time event (DTEVT) occurred.
    Synchronisation is achieved by stopping the ADC at the end of the sampling phase until the trigger occurs. This means that the measurement will freeze if the trigger condition does not occur. Only the trigger for the currently active measurement in the measurement sequence is monitored meaning the order of the enabled measurements in the measurement sequence has to be identical to the order of the triggers occurring. The trigger is only monitored after the end of the sampling extension, meaning “lost” triggers will also stall the measurement.  
    Synchronisation is only performed for the first ADC conversion of a measurement, all subsequent conversions are executed immediately, i.e. their sampling periods end automatically after the selected sampling extension.
  • Setting of input multiplexer:
    The analogue input multiplexer in front of the ADC is set to a specified channel during each measurement.
    The setting can occur either during the sampling phase of the first conversion of a measurement– in which case the input channel becomes effective for the measurement configuration it is specified in. This facilitates easy programming, but by switching the multiplexer during the sampling phase of the ADC a longer sampling extension is required. Alternatively (recommended) the input multiplexer setting can occur after the sampling phase in the conversion phase of the last conversion of the measurement. Then the input multiplexer setting becomes effective for the next measurement, maximising the settling time available for the analogue input signal.
  • Measurement result stored in memory by DMA:
    The result (sum of the conversions) is stored at an address specified relatively to the base address of the measurement sequence.
• ADC timing parameters:
  • ADC clock period
  • Minimum duration of sampling time (2 adc clock periods plus sampling extensions)
  • ADC half clock period where the input multiplexer is set
  • Rising edge of ADC clock can be scheduled with other ADCs (see below)

Figure 2: ADC Timing Diagram (non scheduled adc_clk generation)

Scheduled adc_clk generation

To minimize analogue interference between the ADCs it is advantageous to distribute the active (rising) edges of the four ADC’s adc_clks over time so that a minimum distance (e.g. one system clock cycle) is kept between the rising edges of the adc_clks.

To facilitate this the common MADCC module provides a cyclic counter signal adc_clk_phase counting continuously from 0 to MADCC_CFG.adc_clk_phase_max. Each MADC module can be assigned an adc_clk_phase. It will then delay the generation of the rising adc_clk edge until adc_clk_phase matches its assigned value. By this the active edges of all adc_clks can be distributed over the adc_clk phase given by the MADCC module (round robin scheduling). In a synchronized measurement the adc clock edge initiated by the trigger which ends the sampling phase is never delayed. It is recommended to set the adc clock period used by the MADC modules to be an integer multiple (e.g. 1x) of the adc_clk_phase period of the MADCC module and the sampling extension an integer multiple of the adc_clk, as only then the generated adc_clk periods have a constant length.