SDRAM Custom configuration
The component verification flow is a process where external memory components are getting verified by hint of hardware and software tests. The objective of the process is verifying the timing parameters across the temperature range in order to find the optimal operating point.
All released components for netX 90 SoC are collected here: Supported hardware components netX 90
These tickets contain the component specific parameters for the right adjustment of the component.
By designing a prototype with netX 90 and an external component, These parameters need to be set in the hardware configuraion within netX Studio CDT.
For a SDRAM component the parameters to be set are:
- General Control
- Timing Control
- Mode Register
- Size (MByte)
netX Studio already integrates the overlay files for several memory components, that are released by Hilscher.
A 16-bit SDRAM component may be the IS45S16400J-7BLA2, a 8 MB variant from the manufacturer ISSI, which is currently selectable in the netX Studio SDRAM configuration settings.
Where to find the SDRAM Settings?
Step1: Start your netX Studio CDT Project and select your current or a new Hardware configuration.
Step2: Select the external SDRAM Memory (SDRAM8 for 8-bit SDRAM and SDRAM16 for 16-bit SDRAM) and integrate it into your pinning by Drag & Drop.
Now, the SDRAM configuration window should appear. If not, dopple click or right click on a random SDRAM pin. You can choose between an existing SDRAM component or a Custom setting.
If your specific component is not yet released by Hilscher, you are able to create a custom SDRAM configuration, which is rather simple.
With the following example you could at least start until the CompVerify process is done. The CompVerify later on will basically just verify the timing parameters across the temperature range.
The general configuration of the SDRAM controller will be the same. Perhaps only the timing parameters will be calibrated to ensure the optimal operating point across the temperature range.
Example custom SDRAM configurations
To start a custom SDRAM configuration the data sheet of your component, as well as the netX 90 Register Definition is required.
The netX 90 register definitions as HTML file can be downloaded at Downloads netX 90.
The examples shows, how to select the right values for the Generals Control Register based on the data sheet.
Example 1: General Control for IS45S16400J-7BLA2 from ISSI
Datasheet Values: http://www.issi.com/WW/pdf/42-45S16400J.pdf
- 1M Bits x 16-bit x 4-bank
- Row address A0-A11
- Column address A0-A7
Example 2: General Control for AS4C8M16SA-6BIN from Alliance Memory
Datasheet Values: https://www.alliancememory.com/wp-content/uploads/pdf/dram/128M-AS4C8M16SA.pdf
- 2M Bits x 16-bit x 4-bank
- Row address A0-A11
- Column address A0-A8
Note:
- The netX 90 register definitions as HTML file can be downloaded at Downloads netX 90.
- The parameter settings for the AS4C8M16SA-6BIN type were functionally tested at room temperatures.
The objective of the CompVerify process is verifying the timing parameters across the temperature range in order to find the optimal operating point.
| Bit | Description | Value | Value Description | Example 1: AS4C8M16SA-6BIN (16 MB) | Example 2: IS45S16400J-7BLA2 (8 MB) |
|---|---|---|---|---|---|
| 1-0 | Number of SDRAM device banks and address lines | 00 01 | 2 banks, address (BA0) 4 banks, address lines (BA1, BA0)(default) | 01 | 01 |
| 3-2 | reserved | 0 | 0 | 0 | |
| 5-4 | Number of SDRAM device rows and address lines | 00 01 10 | 2k rows, address lines A0..A10 (default) 4k rows, address lines A0..A11 8k rows, address lines A0..A12 | 01 | 01 |
| 7-6 | reserved | 0 | 0 | 0 | |
| 10-8 | Number of SDRAM device columns and address lines | 000 001 010 011 100 | 256 columns, address lines A0..A7 (default) 512 columns, address lines A0..A8 1k columns, address lines A0..A9 2k columns, address lines A0..A9,A11 4k columns, address lines A0..A9,A11,A12 | 001 | 000 |
| 15-11 | reserved | 0 | 0 | 0 | |
| 16 | SDRAM data bus width | 0 1 | SDRAM data bus is 8 bit wide (default) SDRAM data bus is 16 bit wide | 1 | 1 |
| 17 | SDRAM power down | 0 | If this bit is set, the controller will move SDRAM to power down self refresh mode (no data loss) and stop the external SDRAM clock. Return from power-down mode can be done by clearing this bit. | 0 | 0 |
| 18 | External SDRAM clock enable | 0 1 | SDRAM clock disabled (default) SDRAM clock enabled | 1 | 1 |
| 19 | Global SDRAM controller enable | 0 1 | see sdram_general_ctrl register | 1 | 1 |
| 23-20 | reserved | 0 | 0 | 0 | |
| 25-24 | Refresh request generation mode | 00 01 10 11 | see sdram_general_ctrl register | 00 | 00 |
| 29-26 | reserved | 0 | see sdram_general_ctrl register | 0 | 0 |
| 30 | SDRAM ready | 0 1 | see sdram_general_ctrl register | 0 | 0 |
| 31 | Refresh status flag | 0 1 | see sdram_general_ctrl register | 0 | 0 |
BIN: 0000 0000 0000 1101 0000 0001 0001 0001 HEX: 0x000D0111 → General Control: 0x000D0111 | BIN: 0000 0000 0000 1101 0000 0000 0001 0001 HEX: 0x000D0011 → General Control: 0x000D0011 | ||||
The same procedure needs to be done for the Register "Timing Control" and "Mode Register".
The last value "Size (MByte)" is the size of your component as HEX value in MByte. Thus, a 8 MByte component has the value 0x08, a 16 MByte component the value 0x10 and a 32 MByte component the value 0x20.
| Parameter | AS4C8M16SA-6BIN | IS45S16400J-7BLA2 |
|---|---|---|
| General Control | 0x000D0111 | 0x000D0011 |
| Timing Control | 0x01403251 | 0x01403251 |
| Mode Register | 0x00000022 | 0x00000022 |
| Size (MByte) | 0x10 | 0x08 |
The parameter settings for the AS4C8M16SA-6BIN type were functionally tested at room temperatures.