SPM/DPM data transfer rates

How "fast" is the SPM and DPM Interface?

The diagrams below lists measured execution times of the cifX API function call xChannelIORead() / xChannelIOWrite().
As host controller, a Cortex-M4 based Microcontroller was used, running at 64MHz CPU clock frequency

There is no significant difference between Read and Write access.

The high level xChannelIORead() function call implies overhead. I.e. The measured execution time is not the netto SPI or parallel bus access time.
I.e. during a xChannelIORead()call, there are several SPI / parallel bus access periods, intermittent by breaks where the CPU is working.

Please note: These values are just indications, since the execution time depends on many factors, like host controller performance (CPU clock frequency) , SPI / external bus interface performance, actual configuration of the interface, compiler version and optimization setting, application dependent CPU load of the host controller, etc.

That means, the actual SPM /DPM performance must be evaluated individually for a system.

It is possible to optimize access speed by using low level functions (e.g. cifX Toolkit hardware functions DEV_..() ) instead of the high level cifX API functions xChannelIORead() / xChannelIOWrite(), or even access the SPI / parallel interface directly and handle the handshake flags manually.

Figure 1: SPM - serial Host Interface performance - at different SPI clock frequencies

Figure 2: DPM - parallel Host interface performance