Pin sharing option for 10SPE
According to SPE consortiums, the new physical layer 10BASE-T1L promises to enable Ethernet connectivity based on 10 Mbps over Single Pair Ethernet (10SPE) with extend reach (up to 1000 m), which can be optionally connected to the Media Independent Interface (MII) of the netX 90. The SoC features two flexible communication channels (xC Ch0 and xC Ch1) with MII signals that enable to flexibly adapt in software to emerging standards and future network requirements.
In factory automation, 100BASE-TX is by far the most common physical layer for 100 Mbps based Real-Time Ethernet (100RTE) connectivity. The pinout of the netX 90 is optimised for the integrated 100BASE-TX based dual Ethernet PHY, which requires less pins than any externally MII-connected 10BASE-T1L based Ethernet PHY solution.
The MII signals of the netX 90 are partly shared with application peripherals, including the external 16-bit SDRAM interface, as outlined in the official pinout document at Downloads netX 90. Hilscher's design team tested and verified beforehand a hidden pin sharing option that enables designing applications with external 16-bit SDRAM and 10BASE-T1L based Ethernet PHYs.
The updated pinout document below includes the new pin sharing option 6 and two use case scenarios:
Hilscher is going to release a netX 90 application note until end of Q4-21 that explains in detail how to connect 10BASE-T1L based Ethernet PHY solutions. Furthermore, the hardware configuration tool of the netX Studio CDT will be updated to enable the configuration of the MII pins.