Synchronization Interrupt Signals (IRT, DC Sync)

How am I able to use the IRT / DC Sync events on and inside the application core?

Depending on what you are doing are there several possibilities.

The DPM Handshake Cell interrupts provide you with a DC Sync event via the so called Sync-Hanshake Flags. See FAQ on DPM Interrupts. However, this event has a software overhead and possible jitter.

The Synchronization Interrupt Signal is a hardware signal available to several devices.

• NVIC Application Core Interrupt uses this signal to generate an interrupt inside the application core.
• External MMIO Pins may provide an external microcontroller or peripheral with the synchronization signal.
• Trigger Input of on Chip Peripherals enables a lot of our on chip devices to make use of extended synchronization capabilities.

NVIC:

The sync irq methods may be defined as following. Their name is defined in the CMSIS and implemented weakly with the default interrupt handler.

However, you may modify the trigger device as shown in line 21.

void XCTRIGGER0_IRQHandler(void){
	((trigger_irq_app_Type*) trigger_irq_app_BASE)->trigger_irq_raw_b.xc_trigger_out_edge=1u; //clears sync0 IRQ
	DRV_NVIC_ClearPendingIRQ(trigger_out_edge0_IRQn);
}

void XCTRIGGER1_IRQHandler(void){
	((trigger_irq_app_Type*) trigger_irq_app_BASE)->trigger_irq_raw_b.xc_trigger_out_edge=2u; //clears sync1 IRQ
	DRV_NVIC_ClearPendingIRQ(trigger_out_edge1_IRQn);
}

int main()
{
	((trigger_irq_app_Type*) trigger_irq_app_BASE)->trigger_irq_cfg_b.xc_trigger_out_polarity = 0u;
	((trigger_irq_app_Type*) trigger_irq_app_BASE)->trigger_irq_msk_set_b.xc_trigger_out_edge = 3u; // enables sync0 and sync1 IRQ
	DRV_NVIC_EnableIRQ(trigger_out_edge0_IRQn);
	DRV_NVIC_EnableIRQ(trigger_out_edge1_IRQn);
}

MMIO:

In the hardware config editor you may select the sync event signals as an signal of a MMIO Pad. The Picture below shows how to assign the signal to the pad.

Trigger Input:

In the Register Definition you are able to find the Sync Signal as an trigger input for several devices. In the picture below, the trigger configuration of the EnDat is shown.